1. Field of the Invention
The invention disclosed broadly relates to the field of flip-chip devices, and more particularly relates to the field of semiconductor devices and processes for probing them.
2. Description of the Related Art
Present techniques for connecting an integrated circuit to an integrated circuit package comprise wire bond connections and flip chip connections. Wire bond connections are quite common but the flip chip approach has certain advantages. The wire bonding process comprises mounting an integrated circuit on a substrate with its inactive backside on the substrate and the active side (i.e., where the electrical contacts are) on the side of the die opposite the substrate. Wires are then bonded between the active front side of the integrated circuit and the integrated circuit package. On the other hand, flip chip techniques electrically couple the active side of a die directly to the substrate. The term "flip chip" is used because it is opposite to the traditional approach of placing the inactive backside of an integrated circuit on a substrate. That is, with a flip chip connection the active front side of an integrated circuit is placed on a substrate. An integrated circuit configured for a flip chip connection has solder bumps on wettable metal terminals. The substrate, in turn, has a matching footprint of solder wettable terminals. The solder bumps are aligned and all joints are simultaneously formed by reflowing the solder.
During manufacturing and design, it is often necessary to probe the characteristics of electrical contacts within the integrated circuits (e.g., propagation delays or connection integrity). In the case of wire-bonded designs, there is not much difficulty probing electrical contacts because the wire bonds themselves are easy to probe. There are several techniques that are known to accomplish this. One example is the use of e-beams, wherein the e-beams are directed at the IC package and reflections are measured to determine voltage levels at various points within the IC. In the case of flip-chip designs probing can be more difficult.
As the density of semiconductor devices increases there is a similar increase in the number of connections or I/O points in semiconductor devices. High-end, high pin count and high power devices are demonstrating the limitations of standard package technology, such as: (1) the difficulty to dissipate power (high-power CMOS microprocessor can dissipate as much as 30-50W), (2) the difficulty to bondwire high-pin-count (high-pin count CMOS devices can have from 400 to 800 pins), and (3) the difficulty to meet the speed specifications (flip-chip packages permit up to 15 MHz speed improvement with respect to standard wirebond packages). Thus, the continuously increasing complexity of semiconductor devices is leading to the flip-chip device solution to permit higher pin counts, better power dissipation and higher speed performance due to the lack of bonding wires and capacitance reduction. However, as mentioned above, flip-chip technology creates significant problems in the design analysis phase because there is no longer a capability to acquire waveforms by e-beam methods since the certain metal levels are not accessible. Similar problems associated with use of the flip-chip approach include impossibility to repair and/or correct defects on a single chip. New leading probing technologies (back probing) provide partial solutions for design analysis evaluation but by themselves are not enough to provide the required full design analysis of traditional e-beams methods. Therefore, flip-chip technology is taking place for what is concerning cutting edge technology for semiconductor IC.
However, the characteristics of flip-chips are also the source of some problems. To begin, the top surface of the chip is not accessible from the exterior because it is "soldered" to the package substrate. Only the back of the die (silicon substrate) is visible and accessible for any kind of measurements.
At this point conventional probing techniques, as e-beam and microprobing are not possible any more. In fact these techniques are based on their popularity in the capability to measure voltage values on the metal interconnection. For flip-chip packages this is not possible anymore.
Thus, backprobing technology was developed and presently these systems are basing their capability to probe waveforms internally to the chip using the so-called LVP (laser voltage probing) technology. A laser beam hitting the silicon substrate of the chip (as thinned and coated) and the transistors' junctions. The reflected laser beam is modified by voltage waveform on the junction by this laser beam perturbation. However, some areas in the package under the flip-chip die are still obscured and hence cannot be probed. Therefore, a solution for the above mentioned problem is required.